HTMT-C: Programming A Petaflop Scale Machine Ryan, Amaral, Ruiz, GaoABSTRACT Point design studies for future high performance computers anticipate machines that incorporate new and non-conventional technologies. Such machines will be constructed with a large number of processors, use deep memory hierarchies and exhibit variable latencies. Architectures and programming models must cope with these characteristics. In this paper we present an explicitly multithreaded language developed for the Hybrid Technology Multi-Threaded (HTMT) project. This language implements a new programming model called {\em percolation}. The percolation model, designed to manage data movement within machines that have deep memory hierarchies and unpredictable latencies, requires that instructions of a program segment be paired with the data required by these instructions before they are shipped to the vicinity of the fastest processors in the machine. Under this model, the programmer or compiler may explicitly control the movement of data within the machine's memory hierarchy. We will also briefly describe the HTMT architecture with its supreconducting processors, processor in memory technology, fast optical networks, and holographic memory technology.